1. Field of the Invention
This invention relates to a semiconductor device and a fabrication method thereof, and more particularly to a method for forming a titanium silicide film which is low in electric resist layerance and excellent in heat resist layerance, and a semiconductor device, such as a salicide CMOS transistor, which is reduced in junction leakage currents and suppressed in short-channel effect for raising drive power, and a method of fabricating the same.
2. Related Art
In insulated-gate field effect transistors employed in semiconductor integrated circuits currently available, there is reduction of depletion-layer electric charges carried by a gate electrode relative to the total amount of depletion-layer electric charges, as the device miniaturizes. As a result, the transistor is apt to cause short-channel effects involving lowering of threshold voltage, punch-through, and degradation in sub-threshold characteristics. One factor of such phenomenon is attributable to deep junctions of source and drain regions.
To suppress the short-channel effect, there arises a necessity of making junctions of source and drain regions shallower in commensurate with miniaturization of the device. In PMOS semiconductor devices, there is a general tendency of adopting a surface-channel transistor provided with p-type doping, because the conventional buried-channel transistor with an n-doped gate electrode cannot cope with steping of fine linewidth. With such structure, the gate electrode is built in a dual-gate type. To simplify fabrication steps, the gate electrode is subjected to doping simultaneous with formation of source and drain regions respectively for NMOS and PMOS structures. A self-aligned silicide technique (a salicide technique) also comes to broad utilization for raising drive power of the transistor, accompanied by finer steping and shallower junctions.
A device fabrication method, e.g., shown in FIGS. 26(a)-26(e), is conventionally known as a self-aligned silicide technique (a salicide-transistor technique) (K. Tsukamoto, T. Okamoto, M. Shimizu, T. Matsukawa and H. Harada: Extended Abstracts 16th Int. Conf. Solid State Devices and Materials, Kobe 1984 (Business Center for Academics Societies Japan, Tokyo, 1984) see p. 47). The method of FIGS. 26(a)-26(e) will be explained hereinbelow.
Referring to FIG. 26(a), a silicon semiconductor substrate 601 is formed thereon a field oxide layer 602, a gate oxide film 603, and a gate electrode of polysilicon 604 having side walls thereof covered with an insulation film. The gate electrode contains phosphorus as impurity ions diffused into polysilicon prior to patterning thereof. Then, as shown in FIG. 26(b), an oxide film 606 is deposited and a high concentration of impurity ions are implanted into areas for source and drain through the oxide film 606 with using photo-resist layer as a mask, not shown. As for impurity ions, arsenic ions are employed for an n-channel, while boron is used for a p-channel. Thereafter, a heat treatment for activation is performed, e.g., in a nitrogen ambient at 900xc2x0 C. for 30 minutes for formation of source and drain regions 607. The oxide film 606 is then removed from the surface of the source and rain regions 607 and the gate electrode 604, and thereafter a titanium film 608 is deposited by sputtering in an argon ambient, as shown in FIG. 26(c). Then, a first rapid thermal anneal is performed in a nitrogen ambient at 675xc2x0 C. for approximately 20 seconds, as shown in FIG. 26(d) to react titanium with silicon in the surface layers of the source and drain regions 607 and the gate electrode 604, thereby forming a titanium silicide (TiSi2) of a C49-crystal structure which is stoichiometrically metas-table. On this occasion, the surface of the titanium film 608 alters to a titanium nitride film 609. Etching is then made with using a solution mixture of sulfuric acid and hydrogen peroxide to remove unreacted titanium 608 and a titanium nitride film 609 formed by the first rapid thermal anneal, as shown in FIG. 26(e). Thereafter, a second rapid thermal anneal is performed in an nitrogen ambient at 800xc2x0 C. for approximately 20 seconds to transform the titanium silicide film 610 into a titanium silicide film (TiSi2) of a C54-crystal structure which is stoichiometrically stable.
There is also illustrated in FIGS. 28(a)-28(c) and FIGS. 29(d)-29(g) a conventional fabrication step utilizing a salicide technique for a dual-gate CMOS device. The step is briefly explained with reference to the drawings.
Referring to FIG. 28(a), a silicon semiconductor substrate 801 is first formed with a p-well 802 and an isolation layer 803. Thereafter, a gate dielectric film 804 is formed on the substrate, and a gate electrode 805 is formed to a thickness of, i.e., 2500 angstroms. Then, a thin insulation film 806 is deposited to implant 31p+ ions, thereby forming low-concentration (LDD) region 807, as shown in FIG. 28(b), followed by deposition of a thick insulation film 808 to a thickness of, e.g., 1000 angstroms, as shown in FIG. 28(c) . The thick insulation film is then subjected to isotropic etching to form side wall spacers 809 on side walls of the gate electrode 805, as shown in FIG. 29(d). Subsequently, a thin insulation film 810 is deposited and then 75AS+ ions are implanted in a higher concentration, e.g., 3xc3x971015/cm2, than the 31p+ ions with an implant energy of 40 keV, for forming source and drain regions 811 and n+-doping the gate electrode 805, as shown in FIG. 29(e). Then, annealing is done in a nitrogen ambient at 850xc2x0 C. for 10 minutes and treated by furnace annealing or RTA (Rapid thermal anneal) at 1000xc2x0 C. for 20 seconds, for activating n+ ions and restoring crystal defects in the LDD regions 808, the source and drain regions 811, and the gate electrode 805, as shown in FIG. 29(g). A refractory metal is then deposited by a technique such as sputtering and forming salicide 812 in a self-aligned manner through a heat treatment such as two-step RTA, providing a semiconductor device.
However, the conventional titanium silicide film forming step as above involves problems as given below.
(1) In a reaction system of Ti and Si, impurity ions are implanted through an oxide film, so that oxygen atoms, i.e., oxygen atoms undergoing knock-on upon implant of impurity ions, are inevitably mixed into a silicon semiconductor substrate (See FIG. 27). The mixing of oxygen atoms is particularly prominent when implanting heavy ions, resulting in silicidation reaction in a ternary elenent system of Ti, Si, and O.
(2) Silicidation by the ternary elenent system does not proceed necessary silicidation. Further, SiO2 is preferentially formed in grain boundaries of TiSi2, raising the sheet resist layerance and worsening the heat resist layerance of the titanium silicide film.
(3) Particularly, where silicidation is made in a linewidth finer than the grain size of TiSi2, the above problem (2) is prominent. That is, in silicidation in a linewidth finer than the grain size of TiSi2, transformation C49 into a C54-crystal structure from C49 is inapt to occur by a rapid thermal annealing (an RTA treatment) at 900xc2x0 C. or below, giving a high-resist layerance titanium silicide film. Conversely, where the RTA treatment is performed at a high temperature of 900xc2x0 C. or higher, the transformation of from C49 into the C54-crystal structure is apt to occur. However, there arises worsening of heat resist layerance and causing aggregation of TiSi2 as compared with a broader linewidth of titanium silicide films. Further, with a treatment at such temperature, aggregation begins to occur due to the effect of oxygen atoms even for titanium silicide films with a broader linewidth. There is therefore a problem that aggregation is certain to occur in a finer linewidth of titanium silicide films.
(4) In conventional silicidation, where a heat treatment is performed at such a temperature as to exceed 800xc2x0 C. after formation of a titanium silicide film, aggregation takes place in the titanium silicide film by the effect of oxygen atoms, resulting in diffusion of titanium into the silicon semiconductor substrate. This increases junction current leakage through the source and drain regions and lowers the reliability of the gate oxide film. As for silicidation for a linewidth of finer than the grain size of TiSi2, e.g., silicidation for a gate electrode, there is rise in the sheet resist layerance (resist layerivity of an interconnection) of a titanium silicide film to a level almost equivalent to that of an interconnection without being backed by a titanium silicide film.
(5) In the conventional CMOS forming method, a heat treatment (anneal) is simultaneously done for the n-channel and p-channel. However, the diffusion coefficient of boron in silicon for the p-channel is greater than that of arsenic for the n-channel. Consequently, source and drain regions on the p-channel side become deeper, prominently increasing the short-channel effect.
(6) Where conditions of a heat treatment (anneal) for activation of impurity ions are optimized to meet the p-channel side for suppressing the short-channel effect, crystal-defect restoration on the n-channel side is unsatisfactory, increasing junction current leakage in the n-channel side. Incidentally, an arsenic ion is heavier than an boron ion, effecting heavier damages in implanting.
(7) The junction depth of the source and drain regions is provided shallow by reducing implant energy for suppressing the transistor short-channel effect, lowering the temperature or briefing the time period of a heat treatment. However, a silicide formed is positioned closer to a silicide/silicon interface, the junction leakage current increases.
(8) The polysilicon gate electrode is thick and has low impurity concentration at the interface of the gate electrode and the gate dielectric film even if they are treated by low-energy implant with a low-temperature or brief-time heat treatment. As a result, the gate electrode when applied voltages causes depletion therein, leading to a short-channel effect or reduction of drive power.
In the conventional semiconductor device fabrication method, oxide films as a mask for impurity-ion implant are considered essential for prevention from contamination by other impurities. In a CMOS (complementary MOS) fabrication step, particularly, photo-resist layer masks are necessary for implanting donors and acceptors into respective desired areas. Meanwhile, the photo-resist layer mask includes high content of heavy metals. These heavy metals are contaminants for silicon semiconductor substrate, so that an oxide film is formed over the silicon semiconductor substrate in order not to contact directly the mask with the silicon semiconductor substrate. Under such situations, it has not been emphasized on introduction of oxygen atoms into a silicon semiconductor substrate from an oxide film upon implanting of impurity ions therethrough. This invention has been made by the present inventors based on their finding that the utilization of a silicon nitride film, instead of a silicon oxide film, enables minimization of oxygen atoms introduced from an oxide film upon implanting of impurity ions.
In accordance with a first aspect of the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of:
(a) forming a silicon nitride film over a silicon semiconductor substrate;
(b) implanting impurity ions into a desired area in the surface layer of the substrate through the silicon nitride film, simultaneously incorporation therein of nitrogen atoms and silicon atoms derived from the silicon nitride film.
In accordance with a second aspect of the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of:
(a)xe2x80x2 forming a silicon nitride film over a silicon semiconductor substrate;
(b)xe2x80x2 implanting impurity ions into desired areas of the silicon semiconductor substrate, whereby nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions;
(c)xe2x80x2 removing the silicon nitride film;
(d)xe2x80x2 forming a titanium film over the silicon semiconductor substrate; and
(e)xe2x80x2 subjecting the silicon semiconductor substrate having the titanium film to a heat treatment so as to transform the titanium film into a titanium silicide film containing nitrogen atoms.
In accordance with a third aspect of the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of:
(a)xe2x80x3 forming a silicon nitride film over a silicon semiconductor substrate, the silicon semiconductor substrate having well regions of a first conductivity type and a second conductivity type formed in a surface layer thereof, and a surface layer thereof having gate dielectric films, gate electrodes, and isolation layer formed thereon;
(b)xe2x80x3 implanting impurity ions into desired areas of the silicon semiconductor substrate through the silicon nitride film, wherein
(1) masking the first-conductivity well region with a photo-resist layer and implanting impurity ions of the first conductivity type to cause incorporation of nitrogen atoms and silicon atoms from the silicon nitride film into the second-conductivity well region of the surface layer together with introduction thereinto of impurity ions,
(2) removing the photo-resist layer from the first-conductivity well region and masking the second-conductivity well region with a photo-resist layer to implant impurity ions of the second conductivity type so as to cause incorporation of nitrogen atoms and silicon atoms from the silicon nitride film into the surface layer of the second-conductivity well region together with introduction thereinto of impurity ions,
(3) removing the photo-resist layer from the second-conductivity well region and forming side wall spacers on side walls of respective one of the gate electrodes through the silicon nitride film, and thereafter masking the first-conductivity type well region with a photo-resist layer to implant impurity ions of the second conductivity type so as to cause incorporation of nitrogen atoms and silicon atoms from the silicon nitride film into the surface layer of the second-conductivity well region together with introduction thereinto of impurity ions, and
(4) removing the photo-resist layer from the first-conductivity well region and masking the second-conductivity well region with a photo-resist layer to implant impurity ions of the second conductivity type so as to cause incorporation of nitrogen atoms and silicon atoms from the silicon nitride film into the surface layer of the second-conductivity well region together with introduction thereinto of impurity ions, and then removing the photo-resist layer from the second-conductivity well region;
(c)xe2x80x3 removing the silicon nitride film;
(d)xe2x80x3 forming a titanium film over the silicon semiconductor substrate;
(e)xe2x80x3 subjecting the silicon semiconductor substrate having the titanium film to a first heat treatment so as to transform the titanium film into a titanium silicide film containing nitrogen atoms;
(f) removing unreacted part of the titanium film to leave the titanium silicide film formed by the first heat treatment; and
(g) subjecting the silicon semiconductor substrate having the titanium silicide film so as to transform the silicon nitride film into a TiSi2 C54-crystal structure which is stoichiometrically stable.
In accordance with a fourth aspect of the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of:
(a)xe2x80x2xe2x80x3 forming a first silicon nitride film over a silicon semiconductor substrate, the silicon semiconductor substrate having a gate dielectric film and a gate electrode of polysilicon having a thickness of 100-200 nm formed thereon;
(b)xe2x80x2xe2x80x3 (1) implanting impurity ions of a conductivity type opposite to that of a channel region present beneath the gate electrode into desired areas of the silicon semiconductor substrate so as to incorporate nitride atoms and silicon atoms from the first silicon nitride film into a surface layer of the silicon semiconductor substrate together with introducing of impurity ions thereinto, and
(2) removing the first silicon nitride film and depositing an insulation film to a thickness of 200-300 nm over the silicon semiconductor substrate, subjecting the insulation film to isotropic etching to form side wall spacers on side walls of the gate electrode, and forming a second silicon nitride film over the silicon semiconductor substrate to implant impurity ions of the conductivity type opposite to that of the channel region so as to cause incorporation of nitrogen atoms and silicon atoms from the second silicon nitride film into the gate electrode as well as the surface layer to be formed into source and drain regions of the silicon semiconductor substrate together with introducing impurity ions thereinto;
(c)xe2x80x2xe2x80x3 removing the second silicon nitride film to perform a heat treatment for restoration of crystal defects;
(d)xe2x80x2xe2x80x3 forming a titanium film over the silicon semiconductor substrate; and
(e)xe2x80x2xe2x80x3 subjecting the silicon semiconductor substrate having the titanium film to further heat treatment so as to transform by self-aligning the titanium film into a titanium silicide film containing nitrogen atoms.
Also, in accordance with the present invention, there is provided a semiconductor device fabricated by the third aspect of the invention comprising:
wells of first and second conductivity types formed in a surface layer of a silicon semiconductor substrate;
isolation layers formed on the silicon semiconductor substrate;
gate dielectric films and gate electrodes formed respectively on the first and second conductivity type wells;
titanium silicide films respectively formed on the gate electrodes;
side wall spacers formed on side walls of each of the gate electrodes;
source and drain regions formed in the surface layer on respective sides of each of the gate electrodes;
regions having a junction shallower than that of the source and drain regions respectively formed in the surface layer beneath the side walls; and
titanium silicide film respectively formed on the source and drain regions.
Further, in accordance with the present invention, there is provided a semiconductor device fabricated by the fourth aspect of the invention comprising:
a silicon semiconductor substrate having a gate electrode formed thereon through a gate dielectric film, the gate electrode containing at least polysilicon having a thickness of 100-200 nm;
a titanium silicide film formed on the gate electrode;
side wall spacers formed to a thickness of 150-200 nm on side walls of the gate electrode;
source and drain regions formed to a depth of 120-200 nm in the surface layer on respective sides of the gate electrode, the source and drain regions being of a conductivity type opposite to that of a channel region provided therebetween;
regions having a junction shallower than that of the source and drain regions respectively formed in the surface layer beneath the side walls; and
titanium silicide films respectively formed on the source and drain regions.